It is well known that adjacent devices, such as transistors, in metal oxide semiconductor (MOS) circuits need to be isolated. Several isolation techniques have been developed to accomplish this isolation and include localized oxidation isolation (LOCOS), poly buffered LOCOS, and shallow trench isolation. Although LOCOS is a commonly used technique, shallow trench isolation provides an improved ability to reduce the distance between transistors necessary to isolate the transistors. Therefore, shallow trench isolation advantageously allows for a greater density of transistors in a given area. During shallow trench isolation, trenches separating the transistors are formed into the silicon substrate and typically vary in depth between 0.3M and 0.8M. These trenches can be formed by many methods, but the trenches are commonly provided by anisotropically etching the substrate using dry etching. However, a problem associated with the method of shallow trench isolation is that the top corners of the trench provided by this method typically are sharp and have little rounding. A problem with sharp top trench corner having little rounding is that the corner provides an abrupt transition from the transistor active area to isolation. If a polysilicon gate wraps around into the isolation corner, a parasitic conduction path can occur in the sub-threshold regime. This causes the well-known and undesired "double hump" in the drain current to drain voltage (I-V) curve. One method of producing rounded top corners is by high temperature field oxidation. In this manner, the corner is rounded by growing a thin thermal oxide layer in the trench. However, the degree of rounding of the corners is difficult to control using this process.